NVIDIA's Autonomous Tech set to Supercharge Chip Design

Autonomous AI engineers by NVIDIA are helping to build the next generation of chips and systems, which require complex design cycles.
NVIDIA PhysicsNeMo – a set of agent-friendly libraries – and updated CUDA-X libraries for solvers and quantum chemistry capabilities that support engineering work are now included in the NVIDIA Agent Toolkit, an open foundation including models, tools and skills.
“Engineering has reached an inflection point,” says Timothy Costa, Vice President and General Manager of Computational Engineering at NVIDIA. “AI can now work with tools of physics, simulation and design.
“With NVIDIA Agent Toolkit, developers can build agentic engineers that reason using physics, run complex simulations and generate high-fidelity data to become a new engine for innovation in chip and system design.”
Teaching AI the rules of real-world physics
NVIDIA’s latest toolset brings several technical breakthroughs directly to engineers and software developers.
First, the company is bridging AI with fundamental physics through its PhysicsNeMo libraries. Instead of relying on traditional, slow-moving physics calculations, this technology allows developers to teach AI models how physical forces work – such as airflow around an aircraft wing or heat moving through a engine block.
Engineers can then plug these customisable AI models straight into their everyday design tools, getting fast, reliable feedback without having to wait hours for a simulation to render.
When it comes to raw calculations, physical models rely heavily on sparse linear systems – essentially gigantic mathematical grids where most of the entries are zero, but the non-zero parts are extremely hard to solve.
To tackle this, NVIDIA introduced cuISS, a library of iterative sparse solvers that makes a well-educated guess at a complex calculation and refines it rapidly until it reaches an exact solution. Designed specifically to run across multiple GPUs, cuISS lets developers build ultra-fast, scalable simulation engines for automated engineering workflows.
For problems that require numerical accuracy rather than smart guesses, NVIDIA offers cuDSS, a library focused on direct sparse solvers. Unlike iterative methods, direct solvers work straight through every step of a equation to find an exact answer without trial and error.
This is important in fields like Electronic Design Automation, where tiny, unforgiving circuit layouts and microchip designs leave zero room for margin of error. cuDSS gives developers the high-powered math muscle needed to simulate complex microchips and system architectures seamlessly, even across massive computing clusters.
Finally, NVIDIA is bringing atomic-level science into the fold with cuEST, a tool dedicated to quantum chemistry. Simulating how electrons interact within molecules – known as Electronic Structure Theory – traditionally demands vast computational power, usually limiting accurate tests to tiny clusters of atoms.
cuEST changes this by accelerating complex quantum physics formulas on GPUs. This allows researchers to model much larger, real-world molecular structures – such as next-generation semiconductors, battery materials or pharmaceuticals – while maintaining the deep, sub-atomic accuracy needed to discover new breakthroughs.
- The Vera CPU delivers up to 1.5x higher performance on critical chip verification and simulation tasks
Automating chip design
NVIDIA created Nemotron 3 Ultra, an AI model tuned specifically to help write and test chip blueprints. Working alongside an AI system called ACE-RTLE (developed by NVIDIA Research), this AI can understand chip design problems and write the necessary hardware code better than other open-source AI models available today.
Nemotron 3 Ultra is designed so that technology companies can take the model, run it on their own private servers (on-premises), and train it further using their own confidential data. This gives companies privacy, customisation, and control and efficiency.
Engineers won’t have to change how they work to use it. NVIDIA integrated Nemotron 3 Ultra straight into the major software suites that chip designers rely on every day – including tools from Cadence, Siemens and Synopsys – or developers can access it via open platforms like Hugging Face.
Complementing this AI software, NVIDIA is also deploying its custom Vera CPU to power the underlying hardware computing for these exact workflows.
In early testing with partners like Cadence and Synopsys, the Vera CPU delivered up to 1.5x higher performance on critical chip verification and simulation tasks.
By combining high-performance CPU hardware with specialised AI coding agents, NVIDIA is creating a continuous feedback loop, using its own CPUs and AI tools to accelerate the design of its next-generation processors.
- Cadence, Siemens and Synopsys are some of the industry leaders integrating NVIDIA AI and accelerating computing into engineering workflows spanning design, verification, packaging and systems engineering
Designing microchips usually takes teams of elite engineers thousands of hours. NVIDIA is providing a highly accurate, private AI assistant that automates and speeds up the hardest parts of chip coding without risking a company’s private trade secrets.
“Simulation, verification and implementation technologies play a central role in semiconductor development,” says Ivan Goldwasser, Senior Product Marketing Manager for the NVIDIA Data Center Group.
“Long before a chip reaches manufacturing, engineers spend years validating behaviour, identifying corner cases and refining designs through thousands of iterations.
“Vera combines 88 custom NVIDIA Olympus CPU cores with a high-efficiency LPDDR5X memory subsystem and second generation NVIDIA Scalable Coherent Fabric designed to deliver strong per-core performance, high memory bandwidth and consistent low latency for demanding engineering applications.
“These capabilities are particularly important for workloads that mix latency-sensitive jobs with large-scale regression testing across compute farms. Faster execution can shorten individual verification runs, while greater throughput enables engineers to evaluate more design alternatives and complete more validation within the same development window.”


