Exploring Huawei's Tau Scaling Law for 3D Chips
Rapid advances in computing have pushed transistors toward atomic limits, leaving Moore’s Law with diminishing returns after more than five decades.
Huawei is proposing a new compass for progress with the Tau (τ) Scaling Law, which focuses on reducing signal transmission time across chips and systems.
The principle reframes performance around compressing the time constant τ, the key determinant of frequency, energy efficiency and real-world throughput.
He Tingbo, Co-President of Huawei, unveiled the approach in a keynote at the 2026 International Symposium on Circuits and Systems (ISCAS) in Shanghai, China. Colleagues also refer to the principle as Her’s Law in recognition of her leadership.
LogicFolding moves chip design into 3D
At the heart of Tau is LogicFolding, a methodology that moves chip layouts from flat, two-dimensional grids into three-dimensional architectures.
Traditional 2D floorplans force signals to travel long lateral distances, creating congestion on critical paths and wasting power as data shuttles across the die.
LogicFolding stacks multiple planar circuits vertically, placing core blocks closer together so signals travel shorter distances with lower resistive and capacitive loads.
The result is faster propagation, higher effective density and improved energy efficiency – much like a multi-storey building that moves people between floors more directly than a single-storey sprawl.
Co-optimising devices, circuits, chips and systems
Huawei describes a multi-level co-optimisation that shortens τ from the device layer up to full systems.
At the device level, it is refining transistor and interconnect properties to cut resistance and parasitic capacitance, shrinking delays at the physical foundation.
At the circuit level, LogicFolding reduces critical-path wiring and the RC load of signal propagation, increasing transistor utilisation and circuit performance without relying only on smaller features.
For chips, full-stack coordination aligns software, architecture and silicon for workload-driven control of instruction and data flows, which raises parallelism and real-world efficiency.
The new interconnect protocols such as UnifiedBus target unified memory addressing and native memory semantics for SuperPoDs, cutting latency across large-scale computing.
Smartphones and AI on Huawei’s roadmap
Huawei says it has designed and mass-produced 381 chips over the past six years guided by the τ Scaling Law for a range of sectors and markets.
Kirin processors scheduled for launch in autumn 2026 will be the first commercial chips to adopt the LogicFolding architecture, bringing the 3D approach to consumer devices.
By 2031, Huawei expects high-end chips based on the τ Scaling Law to reach an effective transistor density comparable to 14 Å processes, or about 1.4 nm.
This roadmap sets a course for next-generation smartphones and heavy-duty AI infrastructure, where reducing time – not only size – becomes the lever for sustained gains.
Collaboration to sustain semiconductor progress
Huawei positions Tau as an industry-wide framework and is inviting partners to develop the ecosystem that will make time-centric scaling practical.
The company emphasises open engagement with researchers and engineers to refine LogicFolding tools, packaging, interconnects and software co-design.
It also points to standards work around coherent fabrics and memory semantics as key to system-level benefits in data centres and edge deployments.
Tingbo says: “We believe that openness and collaboration are key to driving ongoing progress in the semiconductor industry. No single company can independently find all the answers along the path of semiconductor evolution.”
